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Shift Registers


In general a shift register is characterized by the following control and data signals, which are fully recognized by XST:

There are different ways to describe shift registers. For example in VHDL you can use:

Consult the VHDL/Verilog language reference manuals for more information.

FPGAs:

Before writing Shift Register behavior it is important to recall that Virtex, Virtex-E, Virtex-II, and Virtex-II Pro have specific hardware resources to implement Shift Registers: SRL16 for Virtex and Virtex-E, and SRLC16 for Virtex-II and Virtex-II Pro. Both are available with or without a clock enable. The following figure shows the pin layout of SRL16E.


The following figure shows the pin layout of SRLC16.


Note Synchronous and asynchronous control signals are not available in the SLRC16x primitives.

However, SRL16 and SRLC16 support only LEFT shift operation for a limited number of IO signals:

It means, that if your shift register does have, for instance, a synchronous parallel load, no SRL16 will be implemented. XST will not try to infer SR4x, SR8x or SR16x macros. It will use specific internal processing which allows it to bring the best final results.

The XST log file reports recognized shift registers when it can be implemented using SRL16.

Log File

The XST log file reports the type and size of recognized shift registers during the macro recognition step:

...

Synthesizing Unit <shift>.

Related source file is shift_registers_1.vhd.

Found 8-bit shift register for signal <tmp<7>>.

Summary:

inferred 1 Shift register(s).

Unit <shift> synthesized.

==============================

HDL Synthesis Report

Macro Statistics

# Shift Registers : 1

8-bit shift register : 1

==============================

...

Related Constraints

A related constraint is shreg_extract.

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Serial Out

Note For this example, XST will infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
SO
Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is 
  port(C, SI : in  std_logic; 
        SO : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C) 
      begin 
        if (C'event and C='1') then 
          for i in 0 to 6 loop 
            tmp(i+1) <= tmp(i); 
          end loop; 
          tmp(0) <= SI; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.

module shift (C, SI, SO); 
input C,SI; 
output SO; 
reg [7:0] tmp; 
 
  always @(posedge C) 
    begin 
      tmp = tmp << 1; 
      tmp[0] = SI; 
    end 
    assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left Register with Negative-Edge Clock, Clock Enable, Serial In, and Serial Out

Note For this example, XST will infer SRL16E_1.

The following table shows pin definitions for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.
IO Pins
Description
C
Negative-Edge Clock
SI
Serial In
CE
Clock Enable (active High)
SO
Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is
  port(C, SI, CE : in  std_logic; 
        SO : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C) 
      begin  
        if (C'event and C='0') then 
          if (CE='1') then 
            for i in 0 to 6 loop 
              tmp(i+1) <= tmp(i); 
            end loop; 
              tmp(0) <= SI; 
          end if; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.

module shift (C, CE, SI, SO); 
input C,SI, CE; 
output SO; 
reg [7:0] tmp; 
 
  always @(negedge C) 
    begin 
      if (CE) 
        begin 
          tmp = tmp << 1; 
          tmp[0] = SI; 
        end 
    end 
    assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous Clear, Serial In, and Serial Out

Note Because this example includes an asynchronous clear, XST will not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
CLR
Asynchronous Clear (active High)
SO
Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is 
  port(C, SI, CLR : in std_logic; 
        SO : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C, CLR) 
      begin 
        if (CLR='1') then 
          tmp <= (others => '0'); 
        elsif (C'event and C='1') then 
          tmp <= tmp(6 downto 0) & SI; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.

module shift (C, CLR, SI, SO); 
input  C,SI,CLR; 
output SO; 
reg [7:0] tmp; 
 
  always @(posedge C or posedge CLR) 
  begin 
    if (CLR) 
      tmp = 8'b00000000; 
    else 
      begin 
        tmp = {tmp[6:0], SI}; 
      end  
  end 
  assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Set, Serial In, and Serial Out

Note Because this example includes an asynchronous clear XST will not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, synchronous set, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
S
synchronous Set (active High)
SO
Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, synchronous set, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is 
  port(C, SI, S : in  std_logic; 
        SO : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C, S) 
      begin 
        if (C'event and C='1') then 
          if (S='1') then 
            tmp <= (others => '1'); 
          else  
            tmp <= tmp(6 downto 0) & SI; 
          end if; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, synchronous set, serial in, and serial out.

module shift (C, S, SI, SO);
input  C,SI,S; 
output SO; 
reg [7:0] tmp; 
 
  always @(posedge C) 
  begin 
    if (S) 
      tmp = 8'b11111111; 
    else 
      begin 
        tmp = {tmp[6:0], SI}; 
      end 
  end 
  assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out

Note For this example XST will infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
PO[7:0]
Parallel Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is  
  port(C, SI : in  std_logic; 
        PO : out std_logic_vector(7 downto 0)); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C) 
      begin  
        if (C'event and C='1') then  
          tmp <= tmp(6 downto 0)& SI; 
        end if; 
    end process; 
    PO <= tmp; 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.

module shift (C, SI, PO); 
input  C,SI; 
output [7:0] PO; 
reg [7:0] tmp; 
 
  always @(posedge C) 
  begin 
    tmp = {tmp[6:0], SI}; 
  end 
  assign PO = tmp; 
endmodule 

8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous Parallel Load, Serial In, and Serial Out

Note For this example XST will infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
ALOAD
Asynchronous Parallel Load (active High)
D[7:0]
Data Input
SO
Serial Output

VHDL Code

Following is VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
entity shift is 
  port(C, SI, ALOAD : in std_logic; 
        D   : in std_logic_vector(7 downto 0); 
        SO  : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin  
    process (C, ALOAD, D) 
      begin 
        if (ALOAD='1') then 
          tmp <= D; 
        elsif (C'event and C='1') then 
          tmp <= tmp(6 downto 0) & SI; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.

module shift (C, ALOAD, SI, D, SO); 
input  C,SI,ALOAD; 
input [7:0] D; 
output SO; 
reg [7:0] tmp; 
 
  always @(posedge C or posedge ALOAD) 
  begin 
    if (ALOAD) 
      tmp = D; 
    else 
      begin 
        tmp = {tmp[6:0], SI}; 
      end 
  end 
  assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out

Note For this example XST will not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
SLOAD
Synchronous Parallel Load (active High)
D[7:0]
Data Input
SO
Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is 
  port(C, SI, SLOAD : in std_logic; 
        D  : in std_logic_vector(7 downto 0); 
        SO : out std_logic); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C) 
      begin 
        if (C'event and C='1') then 
          if (SLOAD='1') then 
            tmp <= D; 
          else 
            tmp <= tmp(6 downto 0) & SI; 
          end if; 
        end if; 
    end process; 
    SO <= tmp(7); 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and serial out.

module shift (C, SLOAD, SI, D, SO); 
input  C,SI,SLOAD; 
input [7:0] D; 
output SO; 
reg [7:0] tmp; 
 
  always @(posedge C) 
  begin 
    if (SLOAD) 
      tmp = D; 
    else 
      begin 
        tmp = {tmp[6:0], SI}; 
      end 
  end 
  assign SO  = tmp[7]; 
endmodule 

8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial In, and Parallel Out

Note For this example XST will not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left/shift-right register with a positive-edge clock, serial in, and serial out.
IO Pins
Description
C
Positive-Edge Clock
SI
Serial In
LEFT_RIGHT
Left/right shift mode selector
PO[7:0]
Parallel Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left/shift-right register with a positive-edge clock, serial in, and serial out.

library ieee; 
use ieee.std_logic_1164.all; 
 
entity shift is 
port(C, SI, LEFT_RIGHT : in std_logic; 
      PO : out std_logic_vector(7 downto 0)); 
end shift; 
architecture archi of shift is 
  signal tmp: std_logic_vector(7 downto 0); 
  begin 
    process (C) 
      begin 
        if (C'event and C='1') then 
          if (LEFT_RIGHT='0') then 
            tmp <= tmp(6 downto 0) & SI; 
          else 
            tmp <= SI & tmp(7 downto 1); 
          end if; 
        end if; 
    end process; 
    PO <= tmp; 
end archi; 

Verilog Code

Following is the Verilog code for an 8-bit shift-left/shift-right register with a positive-edge clock, serial in, and serial out.

module shift (C, SI, LEFT_RIGHT, PO);
input  C,SI,LEFT_RIGHT; 
output PO; 
reg [7:0] tmp; 
 
  always @(posedge C) 
  begin 
    if (LEFT_RIGHT==1'b0) 
      begin 
        tmp = {tmp[6:0], SI}; 
      end 
    else 
      begin 
        tmp = {SI, tmp[6:0]}; 
      end 
  end 
  assign PO  = tmp; 
endmodule 

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