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Accumulators


An accumulator differs from a counter in the nature of the operands of the add and subtract operation:

An inferred accumulator can be up, down or updown. For an updown accumulator, the accumulated data may differ between the up and down mode:

... 
if updown = '1' then 
  a <= a + b; 
else 
  a <= a - c; 
... 

XST can infer an accumulator with the same set of control signals available for counters. (Refer to the "Counters" section of this chapter for more details.)

Log File

The XST log file reports the type and size of recognized accumulators during the macro recognition step:

...

Synthesizing Unit <accum>.

Related source file is accumulators_1.vhd.

Found 4-bit up accumulator for signal <tmp>.

Summary:

inferred 1 Accumulator(s).

Unit <accum> synthesized.

==============================

HDL Synthesis Report

Macro Statistics

# Accumulators : 1

4-bit up accumulator : 1

==============================

...

4-bit Unsigned Up Accumulator with Asynchronous Clear

The following table shows pin definitions for a 4-bit unsigned up accumulator with asynchronous clear.
IO Pins
Description
C
Positive-Edge Clock
CLR
Asynchronous Clear (active High)
D[3:0]
Data Input
Q[3:0]
Data Output

VHDL Code

Following is the VHDL code for a 4-bit unsigned up accumulator with asynchronous clear.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
 
entity accum is 
  port(C, CLR : in  std_logic; 
        D : in std_logic_vector(3 downto 0); 
        Q : out std_logic_vector(3 downto 0)); 
end accum; 
architecture archi of accum is 
  signal tmp: std_logic_vector(3 downto 0); 
  begin 
    process (C, CLR) 
      begin 
        if (CLR='1') then 
          tmp <= "0000"; 
        elsif (C'event and C='1') then 
          tmp <= tmp + D; 
        end if; 
    end process; 
    Q <= tmp; 
end archi; 

Verilog Code

Following is the Verilog code for a 4-bit unsigned up accumulator with asynchronous clear.

module accum (C, CLR, D, Q); 
input C, CLR; 
input  [3:0] D; 
output [3:0] Q; 
reg    [3:0] tmp;  
 
  always @(posedge C or posedge CLR) 
    begin 
      if (CLR) 
        tmp = 4'b0000; 
      else 
        tmp = tmp + D; 
    end 
  assign Q = tmp; 
endmodule 

No constraints are available.


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