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Signed/Unsigned Support


When using VHDL in XST, some macros, such as adders or counters, can be implemented for signed and unsigned values. Depending on the operation and type of the operands, you have to include additional packages in your code. For example, in order to create an Unsigned Adder, you can use the following arithmetic packages and types that operate on unsigned values:
PACKAGE
TYPE
numeric_std
unsigned
std_logic_arith
unsigned
std_logic_unsigned
std_logic_vector

In order to create a Signed Adder you can use arithmetic packages and types that operate on signed values.
PACKAGE
TYPE
numeric_std
signed
std_logic_arith
signed
std_logic_signed
std_logic_vector

Please refer to the IEEE VHDL Manual for details on available types.


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