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Logical Shifters


Xilinx defines a Logical Shifter as a combinatorial circuit with 2 inputs and 1 output:

Moreover, you must adhere to the following conditions when writing your HDL code:

Log File

The XST log file reports the type and size of a recognized logical shifter during the macro recognition step:

...

Synthesizing Unit <lshift>.

Related source file is Logical_Shifters_1.vhd.

Found 8-bit shifter logical left for signal <so>.

Summary:

inferred 1 Combinational logic shifter(s).

Unit <lshift> synthesized.

...

==============================

HDL Synthesis Report

Macro Statistics

# Logic shifters : 1

8-bit shifter logical left : 1

==============================

...

Related Constraints

A related constraint is shift_extract.

Example 1

The following table shows pin descriptions for a logical shifter.
IO pins
Description
D[7:0]
Data Input
SEL
shift distance selector
SO[7:0]
Data Output

VHDL

Following is the VHDL code for a logical shifter.

library ieee;  
 use ieee.std_logic_1164.all;  
 use ieee.numeric_std.all;  
 
 entity lshift is  
  port(DI : in unsigned(7 downto 0);  
      SEL : in unsigned(1 downto 0);  
       SO : out unsigned(7 downto 0));  
 end lshift;  
 architecture archi of lshift is  
   begin  
     with SEL select  
       SO <= DI when "00",  
             DI sll 1 when "01",  
             DI sll 2 when "10",  
             DI sll 3 when others;  
 end archi; 

Verilog

Following is the Verilog code for a logical shifter.

module lshift (DI, SEL, SO);  
input  [7:0] DI;  
input  [1:0] SEL;  
output [7:0] SO;  
reg    [7:0] SO;  
 
  always @(DI or SEL)  
  begin  
    case (SEL)  
      2'b00   : SO <= DI;  
      2'b01   : SO <= DI << 1;  
      2'b10   : SO <= DI << 2;  
      default : SO <= DI << 3;  
    endcase  
  end  
endmodule 

Example 2

XST will not infer a Logical Shifter for this example, as not all of the selector values are presented.
IO pins
Description
D[7:0]
Data Input
SEL
shift distance selector
SO[7:0]
Data Output

VHDL

Following is the VHDL code.

library ieee;  
use ieee.std_logic_1164.all;  
use ieee.numeric_std.all;  
 
entity lshift is  
  port(DI : in unsigned(7 downto 0);  
      SEL : in unsigned(1 downto 0);  
      SO : out unsigned(7 downto 0));  
end lshift;  
architecture archi of lshift is  
  begin  
    with SEL select  
      SO <= DI when "00",  
            DI sll 1 when "01",  
            DI sll 2 when others;  
end archi; 

Verilog

Following is the Verilog code.

module lshift (DI, SEL, SO);  
input  [7:0] DI;  
input  [1:0] SEL;  
output [7:0] SO;  
reg    [7:0] SO;  
 
  always @(DI or SEL)  
  begin  
    case (SEL)  
      2'b00   : SO <= DI;  
      2'b01   : SO <= DI << 1;  
      default : SO <= DI << 2;  
      endcase  
  end  
endmodule 

Example 3

XST will not infer a Logical Shifter for this example, as the value is not incremented by 1 for each consequent binary value of the selector.
IO pins
Description
D[7:0]
Data Input
SEL
shift distance selector
SO[7:0]
Data Output

VHDL

Following is the VHDL code.

library ieee;  
use ieee.std_logic_1164.all;  
use ieee.numeric_std.all;  
 
entity lshift is  
  port(DI : in unsigned(7 downto 0);  
      SEL : in unsigned(1 downto 0);  
      SO : out unsigned(7 downto 0));  
end lshift;  
architecture archi of lshift is  
  begin  
    with SEL select  
      SO <= DI when "00",  
            DI sll 1 when "01",  
            DI sll 3 when "10",  
            DI sll 2 when others;  
end archi; 

Verilog

Following is the Verilog code.

module lshift (DI, SEL, SO);  
input  [7:0] DI;  
input  [1:0] SEL;  
output [7:0] SO;  
reg[7:0] SO;  
 
  always @(DI or SEL)  
  begin  
    case (SEL)  
      2'b00   : SO <= DI;  
      2'b01   : SO <= DI << 1;  
      2'b10   : SO <= DI << 3;  
      default : SO <= DI << 2;  
    endcase  
  end  
endmodule 

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